From 3681de8ab6858752c61047a5966b8f6c695437ce Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 30 Aug 2016 16:57:37 -0500 Subject: mainboard/google/reef: add new memory SKUs Two new SKUs are being utilized for reef DVT. Add the following: Hynix 8GiB using H9HCNNNBPUMLHR-NLE -- id: 4'b0100 Hynix 4GIB using H9HCNNN8KUMLHR-NLE -- id: 4'b0101 BUG=chrome-os-partner:56738 Change-Id: I39ed9e827501939b92cbcce6092302b5a23d1d78 Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/16374 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie Reviewed-by: Furquan Shaikh Reviewed-by: Paul Menzel --- src/mainboard/google/reef/romstage.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'src/mainboard/google/reef/romstage.c') diff --git a/src/mainboard/google/reef/romstage.c b/src/mainboard/google/reef/romstage.c index 964dee42cf..d7ec5b263b 100644 --- a/src/mainboard/google/reef/romstage.c +++ b/src/mainboard/google/reef/romstage.c @@ -113,6 +113,26 @@ static const struct lpddr4_sku skus[] = { .part_num = "MT53B256M32D1NP", .disable_periodic_retraining = 1, }, + /* + * H9HCNNNBPUMLHR-NLE - both logical channels. While the parts + * are listed at 16Gb there are 2 ranks per channel so indicate the + * density as 8Gb per rank. + */ + [4] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .ch0_dual_rank = 1, + .ch1_dual_rank = 1, + .part_num = "H9HCNNNBPUMLHR", + }, + /* H9HCNNN8KUMLHR-NLE - both logical channels */ + [5] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .part_num = "H9HCNNN8KUMLHR", + }, /* K4F8E304HB-MGCH - both logical channels */ [PROTO_SKU] = { .speed = LP4_SPEED_2400, -- cgit v1.2.3