From dfb373541b71e4a8a41d1b4b5407c47ca0d9b5bd Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Wed, 3 Aug 2016 17:15:02 -0700 Subject: google/reef: Enable I2C2 for use in bootblock Enable I2C bus 2 for early init so it can be used by vboot for TPM communication for verifying the memory init code. BUG=chrome-os-partner:53336 BRANCH=none TEST=build and boot on reef Change-Id: Id4940ab01d8ccf288ab0a7a9a2f19867ed464e8d Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/16059 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/google/reef/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/mainboard/google/reef/devicetree.cb') diff --git a/src/mainboard/google/reef/devicetree.cb b/src/mainboard/google/reef/devicetree.cb index 5e68d3720c..ea3b20f2e2 100644 --- a/src/mainboard/google/reef/devicetree.cb +++ b/src/mainboard/google/reef/devicetree.cb @@ -43,6 +43,9 @@ chip soc/intel/apollolake register "gpe0_dw2" = "PMC_GPE_N_63_32" register "gpe0_dw3" = "PMC_GPE_SW_31_0" + # Enable I2C2 bus early for TPM access + register "i2c[2].early_init" = "1" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF -- cgit v1.2.3