From 57f221e6c47261e82bc21f6baa25dfa17b097f5a Mon Sep 17 00:00:00 2001 From: Shaunak Saha Date: Tue, 12 Jul 2016 16:03:29 -0700 Subject: google/reef: Enable DPTF in mainboard This patch enables DPTF support for Google Reef platform, adds the ASL settings specific to Reef boards. BUG=chrome-os-partner:53096 TEST=Verify that the thermal zones are enumerated under /sys/class/thermal in Reef boards. Navigate to /sys/class/thermal, and verify that a thermal zone of type TCPU exists there. Change-Id: Ib43e4e9dd0d92fffc1b2c8459c552acd04ca0150 Signed-off-by: Shaunak Saha Reviewed-on: https://review.coreboot.org/15640 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- src/mainboard/google/reef/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/mainboard/google/reef/devicetree.cb') diff --git a/src/mainboard/google/reef/devicetree.cb b/src/mainboard/google/reef/devicetree.cb index 02a438468a..5e68d3720c 100644 --- a/src/mainboard/google/reef/devicetree.cb +++ b/src/mainboard/google/reef/devicetree.cb @@ -31,6 +31,9 @@ chip soc/intel/apollolake # 0x1C[6:0] stands for 28*125 = 3500 pSec delay for HS200 register "emmc_rx_cmd_data_cntl2" = "0x1001C" + # Enable DPTF + register "dptf_enable" = "1" + # GPE configuration # Note that GPE events called out in ASL code rely on this # route, i.e., if this route changes then the affected GPE -- cgit v1.2.3