From 17721be11a64b82d1d2bb4165bd3bf8380016fdf Mon Sep 17 00:00:00 2001 From: Michael Niewöhner Date: Mon, 21 Dec 2020 17:09:08 +0100 Subject: mb/google/reef: do LPC/eSPI pad configuration at board-level MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Do LPC/eSPI pad configuration at board-level to match other platforms. This is done by adding missing pads to the bootblock gpio table. The soc code gets dropped in CB:49410. Change-Id: I95993b1bd4f1fd8b4ac7b21fb89ec4d196b0240a Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/49412 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/mainboard/google/reef/bootblock.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/mainboard/google/reef/bootblock.c') diff --git a/src/mainboard/google/reef/bootblock.c b/src/mainboard/google/reef/bootblock.c index 3e9f51afd0..577dae507d 100644 --- a/src/mainboard/google/reef/bootblock.c +++ b/src/mainboard/google/reef/bootblock.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include @@ -12,7 +11,6 @@ void bootblock_mainboard_init(void) const struct pad_config *pads; size_t num; - lpc_configure_pads(); pads = variant_early_gpio_table(&num); gpio_configure_pads(pads, num); mainboard_ec_init(); -- cgit v1.2.3