From 18ea2d3fbdf89f60a74dc8aabfdb2aa4d3475754 Mon Sep 17 00:00:00 2001
From: Julius Werner <jwerner@chromium.org>
Date: Tue, 7 Oct 2014 16:42:17 -0700
Subject: baytrail: Change all SoC headers to <soc/headername.h> system

This patch aligns baytrail to the new SoC header include scheme.

BUG=None
TEST=Tested with whole series. Compiled Rambi.

Change-Id: I0f0a894f6f33449756582eefa0b50bae545220db
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1216a86538517c03a7e5bca547d08ff3dbcaa083
Original-Change-Id: If5d2a609354b3d773aa3d482e682ab97422fd9d5
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/222026
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9363
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
---
 src/mainboard/google/rambi/acpi_tables.c   | 6 +++---
 src/mainboard/google/rambi/chromeos.c      | 2 +-
 src/mainboard/google/rambi/fadt.c          | 2 +-
 src/mainboard/google/rambi/gpio.c          | 2 +-
 src/mainboard/google/rambi/irqroute.h      | 6 +++---
 src/mainboard/google/rambi/mainboard.c     | 2 +-
 src/mainboard/google/rambi/mainboard_smi.c | 4 ++--
 src/mainboard/google/rambi/romstage.c      | 6 +++---
 src/mainboard/google/rambi/w25q64.c        | 2 +-
 9 files changed, 16 insertions(+), 16 deletions(-)

(limited to 'src/mainboard/google/rambi')

diff --git a/src/mainboard/google/rambi/acpi_tables.c b/src/mainboard/google/rambi/acpi_tables.c
index 890e1df966..981116bfe4 100644
--- a/src/mainboard/google/rambi/acpi_tables.c
+++ b/src/mainboard/google/rambi/acpi_tables.c
@@ -30,9 +30,9 @@
 #include <device/pci_ids.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/msr.h>
-#include <baytrail/acpi.h>
-#include <baytrail/nvs.h>
-#include <baytrail/iomap.h>
+#include <soc/acpi.h>
+#include <soc/nvs.h>
+#include <soc/iomap.h>
 
 extern const unsigned char AmlCode[];
 
diff --git a/src/mainboard/google/rambi/chromeos.c b/src/mainboard/google/rambi/chromeos.c
index 3ab30347ca..31d7de0fbe 100644
--- a/src/mainboard/google/rambi/chromeos.c
+++ b/src/mainboard/google/rambi/chromeos.c
@@ -22,7 +22,7 @@
 #include <arch/io.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <baytrail/gpio.h>
+#include <soc/gpio.h>
 
 #if CONFIG_EC_GOOGLE_CHROMEEC
 #include "ec.h"
diff --git a/src/mainboard/google/rambi/fadt.c b/src/mainboard/google/rambi/fadt.c
index 0bd33e14a1..dfd258fa8b 100644
--- a/src/mainboard/google/rambi/fadt.c
+++ b/src/mainboard/google/rambi/fadt.c
@@ -18,7 +18,7 @@
  */
 
 #include <string.h>
-#include <baytrail/acpi.h>
+#include <soc/acpi.h>
 
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {
diff --git a/src/mainboard/google/rambi/gpio.c b/src/mainboard/google/rambi/gpio.c
index 77f56f7c94..45f536db21 100644
--- a/src/mainboard/google/rambi/gpio.c
+++ b/src/mainboard/google/rambi/gpio.c
@@ -18,7 +18,7 @@
  */
 
 #include <stdlib.h>
-#include <baytrail/gpio.h>
+#include <soc/gpio.h>
 #include "irqroute.h"
 
 /* TODO(SHAWNN): Modify gpios labeled 'INT' for interrupt handling */
diff --git a/src/mainboard/google/rambi/irqroute.h b/src/mainboard/google/rambi/irqroute.h
index 0f4ca17acc..074e47093e 100644
--- a/src/mainboard/google/rambi/irqroute.h
+++ b/src/mainboard/google/rambi/irqroute.h
@@ -17,9 +17,9 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#include <soc/intel/baytrail/baytrail/irq.h>
-#include <soc/intel/baytrail/baytrail/pci_devs.h>
-#include <soc/intel/baytrail/baytrail/pmc.h>
+#include <soc/irq.h>
+#include <soc/pci_devs.h>
+#include <soc/pmc.h>
 
 #define PCI_DEV_PIRQ_ROUTES \
 	PCI_DEV_PIRQ_ROUTE(GFX_DEV,  A, B, C, D), \
diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c
index 7128448e33..1266390930 100644
--- a/src/mainboard/google/rambi/mainboard.c
+++ b/src/mainboard/google/rambi/mainboard.c
@@ -36,7 +36,7 @@
 #include <smbios.h>
 #include "ec.h"
 #include "onboard.h"
-#include <baytrail/gpio.h>
+#include <soc/gpio.h>
 #include <bootstate.h>
 
 void mainboard_suspend_resume(void)
diff --git a/src/mainboard/google/rambi/mainboard_smi.c b/src/mainboard/google/rambi/mainboard_smi.c
index bd7646899f..7afdd2f1a5 100644
--- a/src/mainboard/google/rambi/mainboard_smi.c
+++ b/src/mainboard/google/rambi/mainboard_smi.c
@@ -25,8 +25,8 @@
 #include <ec/google/chromeec/ec.h>
 #include "ec.h"
 
-#include <baytrail/nvs.h>
-#include <baytrail/pmc.h>
+#include <soc/nvs.h>
+#include <soc/pmc.h>
 
 /* The wake gpio is SUS_GPIO[0]. */
 #define WAKE_GPIO_EN SUS_GPIO_EN0
diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c
index 7c505e73b3..0f431d93ae 100644
--- a/src/mainboard/google/rambi/romstage.c
+++ b/src/mainboard/google/rambi/romstage.c
@@ -21,9 +21,9 @@
 #include <string.h>
 #include <cbfs.h>
 #include <console/console.h>
-#include <baytrail/gpio.h>
-#include <baytrail/mrc_wrapper.h>
-#include <baytrail/romstage.h>
+#include <soc/gpio.h>
+#include <soc/mrc_wrapper.h>
+#include <soc/romstage.h>
 
 /*
  * RAM_ID[2:0] are on GPIO_SSUS[39:37]
diff --git a/src/mainboard/google/rambi/w25q64.c b/src/mainboard/google/rambi/w25q64.c
index dbc26e4732..9692b4c10a 100644
--- a/src/mainboard/google/rambi/w25q64.c
+++ b/src/mainboard/google/rambi/w25q64.c
@@ -18,7 +18,7 @@
  */
 
 #include <string.h>
-#include <baytrail/spi.h>
+#include <soc/spi.h>
 
 /*
  * SPI lockdown configuration W25Q64FW.
-- 
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