From ce0a56419854d8c2bd0fac401c76139106fc4dd8 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Thu, 12 Jan 2017 12:19:21 -0600 Subject: Combine Baytrail ChromeOS devices using variant scheme Combine existing boards google/enguarde and google/ninja using their common reference board google/rambi as a baseboard. Variants contain board specific data: - DPTF ACPI components - I2C ACPI devices - RAM config / SPD data - devicetree config - GPIOs - board-specific HW components (e.g., LAN) Additionally, some minor cleanup/changes were made: - remove unused ACPI trackpad/touchscreen devices - correct I2C addresses in SMBIOS entries - clean up comment formatting - remove ACPI device for unused light sensor - switch I2C ACPI devices from edge to level triggered interrupts, for better compatibility/functionality (and to be consistent with other recently-upstreamed ChromeOS devices) The existing enguarde and ninja boards are removed. Variant setup modeled after google/auron Change-Id: Iae7855af9a224fd4cb948b854494e39b545ad449 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/18129 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/mainboard/google/rambi/romstage.c | 20 ++------------------ 1 file changed, 2 insertions(+), 18 deletions(-) (limited to 'src/mainboard/google/rambi/romstage.c') diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c index e9dba818c1..152d5e6c76 100644 --- a/src/mainboard/google/rambi/romstage.c +++ b/src/mainboard/google/rambi/romstage.c @@ -20,29 +20,13 @@ #include #include #include - -/* - * RAM_ID[2:0] are on GPIO_SSUS[39:37] - * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz - * 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz - * 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz - * 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz - * 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz - * 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz - */ -static const uint32_t dual_channel_config = - (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3); - -#define SPD_SIZE 256 -#define GPIO_SSUS_37_PAD 57 -#define GPIO_SSUS_38_PAD 50 -#define GPIO_SSUS_39_PAD 58 +#include static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) { int ram_id = 0; - /* The ram_id[2:0] pullups on rambi are too large for the default 20K + /* The ram_id[2:0] pullups are too large for the default 20K * pulldown on the pad. Therefore, disable the internal pull resistor to * read high values correctly. */ ssus_disable_internal_pull(GPIO_SSUS_37_PAD); -- cgit v1.2.3