From 3fbf671194a8f1469bf0e122fed8e8da23893ac9 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Mon, 11 Nov 2013 14:55:47 -0600 Subject: rambi: mainboard EC - SCI and SMI fixes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As rambi is a baytrail board it doesn't have a dedicated wake pin. Therefore, one needs to enable the proper GPIO to wake up the sytem before going into S3. BUG=chrome-os-partner:23505 BRANCH=None TEST=Put system into S3. Keyboard press created wake event. Also, typed 'lidclose' on EC console while at recovery screen. Machine properly shutdown. Change-Id: Ic67b6bce93d57c620f498505d83197e4ae34a07d Signed-off-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/176392 Reviewed-on: http://review.coreboot.org/4959 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/google/rambi/mainboard_smi.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) (limited to 'src/mainboard/google/rambi/mainboard_smi.c') diff --git a/src/mainboard/google/rambi/mainboard_smi.c b/src/mainboard/google/rambi/mainboard_smi.c index ac5c841030..09a858039d 100644 --- a/src/mainboard/google/rambi/mainboard_smi.c +++ b/src/mainboard/google/rambi/mainboard_smi.c @@ -28,6 +28,9 @@ #include #include +/* The wake gpio is SUS_GPIO[0]. */ +#define WAKE_GPIO_EN SUS_GPIO_EN0 + int mainboard_io_trap_handler(int smif) { switch (smif) { @@ -67,7 +70,7 @@ static uint8_t mainboard_smi_ec(void) /* Go to S5 */ pm1_cnt = inl(pmbase + PM1_CNT); - pm1_cnt |= SLP_TYP | (SLP_TYP_S5 << SLP_TYP_SHIFT); + pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT); outl(pm1_cnt, pmbase + PM1_CNT); break; } @@ -75,9 +78,11 @@ static uint8_t mainboard_smi_ec(void) return cmd; } -void mainboard_smi_gpi(uint32_t gpi_sts) +/* The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that + * this includes the enable bits in the lower 16 bits. */ +void mainboard_smi_gpi(uint32_t alt_gpio_smi) { - if (gpi_sts & (1 << EC_SMI_GPI)) { + if (alt_gpio_smi & (1 << EC_SMI_GPI)) { /* Process all pending events */ while (mainboard_smi_ec() != 0); } @@ -97,6 +102,8 @@ void mainboard_smi_sleep(uint8_t slp_typ) /* Enable wake events */ google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); + /* Enable wake pin in GPE block. */ + enable_gpe(WAKE_GPIO_EN); break; case 5: if (smm_get_gnvs()->s5u0 == 0) -- cgit v1.2.3