From 8b126e8b7235641d3003fdd220b0fe2377361035 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sun, 17 Sep 2023 17:36:23 -0500 Subject: mb/google/puff: Set early GPIOs to enable bootblock console Without the PCH UART GPIOs set early, there is no serial console output until ramstage. Add them to the early GPIOs for all puff variants. TEST=build/boot google/puff (wyvern) with serial console enabled, verify console output starts in bootblock. Change-Id: Ica0506b2b80e4fac0d3ca11b4cfdd128ce424b36 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/78029 Reviewed-by: Nick Vaccaro Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/mainboard/google/puff/variants/duffy/gpio.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/mainboard/google/puff/variants/duffy/gpio.c') diff --git a/src/mainboard/google/puff/variants/duffy/gpio.c b/src/mainboard/google/puff/variants/duffy/gpio.c index 996edc4fc7..f50620e358 100644 --- a/src/mainboard/google/puff/variants/duffy/gpio.c +++ b/src/mainboard/google/puff/variants/duffy/gpio.c @@ -94,6 +94,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C8 : UART_PCH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART_PCH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* C14 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 0, DEEP), /* PCH_WP_OD */ -- cgit v1.2.3