From ea4649f65fece2e14a3f2b0d1b4f5835a76a1141 Mon Sep 17 00:00:00 2001 From: Rizwan Qureshi Date: Wed, 6 Sep 2017 19:08:23 +0530 Subject: mb/google/poppy: enable AER for PCIe root port 0 Enable PCIe Advanced Error Reporting for PCIe root port 0. BUG=b:64798078 TEST="lspci" shows that AER is enabled in the capabilities list. Change-Id: I8a818a9539b8d4f103d551ffd59713c9bbbc13ce Signed-off-by: Rizwan Qureshi Reviewed-on: https://review.coreboot.org/21425 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/poppy/variants/baseboard/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mainboard/google/poppy') diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 5b81fc0d49..0bd2efc92c 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -152,6 +152,8 @@ chip soc/intel/skylake register "PcieRpClkReqSupport[0]" = "1" # RP 1 uses SRCCLKREQ1# register "PcieRpClkReqNumber[0]" = "1" + # RP 1, Enable Advanced Error Reporting + register PcieRpAdvancedErrorReporting[0] = "1" register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port -- cgit v1.2.3