From 40b41826e125fd726cec1369676d53704add3a0b Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Wed, 7 Nov 2018 13:19:36 -0800 Subject: mb/google/poppy/variant/atlas: config GPP_F10 to use PLTRST GPIO's that use GPI_APIC setting with DEEP causes an IRQ storm after S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic reset over PLTRST to prevent IRQ storm after S3 resume and hence configuring GPP_F10 (HP_IRQ_GPIO) to use PLTRST. BUG=none TEST=none Change-Id: Idc6c42cb4dc6e8eb368d605c83f584f4c69077dc Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/29540 Reviewed-by: Furquan Shaikh Reviewed-by: caveh jalali Reviewed-by: Pratikkumar V Prajapati Tested-by: build bot (Jenkins) --- src/mainboard/google/poppy/variants/atlas/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/google/poppy') diff --git a/src/mainboard/google/poppy/variants/atlas/gpio.c b/src/mainboard/google/poppy/variants/atlas/gpio.c index 58f7fc5943..02c145c624 100644 --- a/src/mainboard/google/poppy/variants/atlas/gpio.c +++ b/src/mainboard/google/poppy/variants/atlas/gpio.c @@ -273,7 +273,7 @@ static const struct pad_config gpio_table[] = { /* F9 : I2C4_SCL ==> PCH_I2C4_AUDIO_1V8_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* F10 : I2C5_SDA ==> HP_IRQ_GPIO */ - PAD_CFG_GPI_APIC(GPP_F10, 20K_PU, DEEP), + PAD_CFG_GPI_APIC(GPP_F10, 20K_PU, PLTRST), /* F11 : I2C5_SCL ==> SPKR_RST_L */ PAD_CFG_GPO(GPP_F11, 1, RSMRST), /* F12 : EMMC_CMD */ -- cgit v1.2.3