From 085649440bb1604d8492156838813938df10eb83 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 4 Jun 2021 18:55:03 +0200 Subject: mb/google/poppy: Do not let FSP-S init UART 0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit FSP-S configures the GPIOs for enabled SerialIO devices. However, Poppy boards only enable UART 0 because it's function 0 of PCI device 30, and the PCI specification requires that function 0 of multifunction devices be implemented if other functions are implemented as well. Nautilus got remedied in commit 8a1f095e50e068e42d378f47c79467e7b6295b7b (mb/google/poppy/variants/nautilus: Update camera power enable GPIOs) by using `PchSerialIoSkipInit` for UART 0, which tells FSP to not touch the SerialIO device. This way, it remains enabled and the GPIO settings will not be overwritten by FSP. However, not all variants do this, but use some UART 0 pads as GPIOs. To prevent any issues, configure UART 0 as `PchSerialIoSkipInit` on all the variants. Change-Id: I7e3a61769ef9e3b348ce84c663f67d3c4c5d9485 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/55236 Reviewed-by: Michael Niewöhner Reviewed-by: Matt DeVillier Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/google/poppy/variants/baseboard/devicetree.cb | 2 +- src/mainboard/google/poppy/variants/nami/devicetree.cb | 2 +- src/mainboard/google/poppy/variants/rammus/devicetree.cb | 2 +- src/mainboard/google/poppy/variants/soraka/devicetree.cb | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'src/mainboard/google/poppy') diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 249183b420..ebbb12f973 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -236,7 +236,7 @@ chip soc/intel/skylake [PchSerialIoIndexI2C5] = PchSerialIoPci, [PchSerialIoIndexSpi0] = PchSerialIoDisabled, [PchSerialIoIndexSpi1] = PchSerialIoDisabled, - [PchSerialIoIndexUart0] = PchSerialIoPci, + [PchSerialIoIndexUart0] = PchSerialIoSkipInit, [PchSerialIoIndexUart1] = PchSerialIoDisabled, [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 51da81aa94..34163efc51 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -256,7 +256,7 @@ chip soc/intel/skylake [PchSerialIoIndexI2C5] = PchSerialIoDisabled, [PchSerialIoIndexSpi0] = PchSerialIoPci, [PchSerialIoIndexSpi1] = PchSerialIoPci, - [PchSerialIoIndexUart0] = PchSerialIoPci, + [PchSerialIoIndexUart0] = PchSerialIoSkipInit, [PchSerialIoIndexUart1] = PchSerialIoDisabled, [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index b3812d704f..f2dc5b6b3b 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -217,7 +217,7 @@ chip soc/intel/skylake [PchSerialIoIndexI2C5] = PchSerialIoPci, [PchSerialIoIndexSpi0] = PchSerialIoPci, [PchSerialIoIndexSpi1] = PchSerialIoDisabled, - [PchSerialIoIndexUart0] = PchSerialIoPci, + [PchSerialIoIndexUart0] = PchSerialIoSkipInit, [PchSerialIoIndexUart1] = PchSerialIoDisabled, [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index b44e867b5b..745d72ce32 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -237,7 +237,7 @@ chip soc/intel/skylake [PchSerialIoIndexI2C5] = PchSerialIoPci, [PchSerialIoIndexSpi0] = PchSerialIoDisabled, [PchSerialIoIndexSpi1] = PchSerialIoDisabled, - [PchSerialIoIndexUart0] = PchSerialIoPci, + [PchSerialIoIndexUart0] = PchSerialIoSkipInit, [PchSerialIoIndexUart1] = PchSerialIoDisabled, [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" -- cgit v1.2.3