From 9c12e90819c3a7955adf9de2fa82cc652ae6a76f Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sun, 17 Dec 2017 20:31:18 -0800 Subject: mb/google/poppy/variants/nautilus: Enable AER and LTR for root port 1 Similar to other KBL projects, this change enables AER and LTR for root port 1 on poppy. BUG=b:65570878 Change-Id: Iadad3d2fc46cbba575a776071305925c529a6760 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/22923 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/google/poppy/variants/nautilus/devicetree.cb | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/mainboard/google/poppy/variants') diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index ac3bd1dc45..46b0946c2b 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -157,6 +157,10 @@ chip soc/intel/skylake register "PcieRpClkReqSupport[0]" = "1" # RP 1 uses SRCCLKREQ1# register "PcieRpClkReqNumber[0]" = "1" + # RP 1, Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[0]" = "1" + # RP 1, Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[0]" = "1" register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port -- cgit v1.2.3