From 6c83a71b0a803c922b02b613e927d4c49b944c32 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Sun, 23 Jun 2024 00:25:18 +0200 Subject: skl mainboards/dt: Move usb{2,3}_ports settings into XHCI device scope MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I22ba991a9d559b0ecc7b3ceddcfd099890dd6c3a Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/83171 Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai Reviewed-by: Marvin Evers Reviewed-by: Erik van den Bogaert Reviewed-by: Michael Niewöhner Reviewed-by: Jonathon Hall --- .../google/poppy/variants/nocturne/devicetree.cb | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) (limited to 'src/mainboard/google/poppy/variants/nocturne/devicetree.cb') diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 1ef0b454ab..140f5f864b 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -147,16 +147,6 @@ chip soc/intel/skylake register "PcieRpAdvancedErrorReporting[8]" = "1" register "PcieRpLtrEnable[8]" = "1" - # USB 2.0 - register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 - register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2 - register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" # pogo port - - # USB 3.0 - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 - # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -247,6 +237,18 @@ chip soc/intel/skylake device ref sa_thermal on end device ref imgu on end device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_LONG(OC0), // Type-C Port 1 + [2] = USB2_PORT_SHORT(OC_SKIP), // Bluetooth + [4] = USB2_PORT_LONG(OC1), // Type-C Port 2 + [6] = USB2_PORT_LONG(OC_SKIP), // pogo port + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), // Type-C Port 1 + [1] = USB3_PORT_DEFAULT(OC1), // Type-C Port 2 + }" + chip drivers/usb/acpi register "desc" = ""Root Hub"" register "type" = "UPC_TYPE_HUB" -- cgit v1.2.3