From c077b2274b661fb57ffed66b105ece88e30c73b2 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 1 Aug 2019 10:50:35 +0530 Subject: soc/intel/skylake: Make use of common thermal code for SKL This patch ensures skylake soc is using common thermal code from intel common block. TEST=Build and boot soraka Change-Id: I0812daa3536051918ccac973fde8d7f4f949609d Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/34648 Reviewed-by: Furquan Shaikh Reviewed-by: Aamir Bohra Tested-by: build bot (Jenkins) --- src/mainboard/google/poppy/variants/nami/devicetree.cb | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'src/mainboard/google/poppy/variants/nami') diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 7c11ea19c4..3d37eda207 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -219,6 +219,7 @@ chip soc/intel/skylake #| I2C1 | Trackpad | #| I2C2 | Pen | #| I2C3 | Audio | + #| pch_thermal_trip | PCH Trip Temperature | #+-------------------+---------------------------+ register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, @@ -263,6 +264,7 @@ chip soc/intel/skylake .sda_hold = 36, }, }, + .pch_thermal_trip = 75, }" # Must leave UART0 enabled or SD/eMMC will not work as PCI @@ -285,9 +287,6 @@ chip soc/intel/skylake register "tcc_offset" = "3" # TCC of 97C register "psys_pmax" = "101" - # PCH Trip Temperature in degree C - register "pch_trip_temp" = "75" - device cpu_cluster 0 on device lapic 0 on end end -- cgit v1.2.3