From dcddc53fde2d559beef998d3c17e9b7a227e3665 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Sun, 23 Jun 2024 03:39:24 +0200 Subject: skl mainboards/dt: Move genx_dec settings into LPC device scope MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Iecb4851bedb7c9ed7793763d80acbcbb068e8832 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/83172 Reviewed-by: Michael Niewöhner Reviewed-by: Jonathon Hall Reviewed-by: Erik van den Bogaert Reviewed-by: Eric Lai Reviewed-by: Marvin Evers Tested-by: build bot (Jenkins) --- src/mainboard/google/poppy/variants/atlas/devicetree.cb | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'src/mainboard/google/poppy/variants/atlas') diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 8b821f6ecf..85a1e23a70 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -27,12 +27,6 @@ chip soc/intel/skylake register "gpe0_dw1" = "GPP_B" register "gpe0_dw2" = "GPP_E" - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" - # Enable DPTF register "dptf_enable" = "1" @@ -363,6 +357,12 @@ chip soc/intel/skylake device ref sdio off end device ref sdxc off end device ref lpc_espi on + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + chip ec/google/chromeec device pnp 0c09.0 on end end -- cgit v1.2.3