From 691d58f9996d2ff3820b2c08646e98f16bbde2ee Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 11 Aug 2021 13:42:40 +0200 Subject: nb/intel/sandybridge: Add a chipset devicetree This only moves CPU configuration to a common place. Other PCI devices can be done in follow-ups. Change-Id: I9c5b6f25b779e28b6719cf70455ff0f1a916ad87 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/56912 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/google/parrot/devicetree.cb | 12 ------------ 1 file changed, 12 deletions(-) (limited to 'src/mainboard/google/parrot') diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index 6850cf2c6d..7c1cc8184d 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -19,18 +19,6 @@ chip northbridge/intel/sandybridge register "max_mem_clock_mhz" = "666" - device cpu_cluster 0 on - chip cpu/intel/model_206ax - # Magic APIC ID to locate this chip - device lapic 0 on end - device lapic 0xacac off end - - register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) - register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) - register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) - end - end - device domain 0 on device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller -- cgit v1.2.3