From 4923c399f3ca1120aba3f4d5e16eaa2b815ea2aa Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Wed, 19 Feb 2014 15:05:15 -0800 Subject: google/panther: Force enable ASPM on PCIe Root Port 4 BUG=chrome-os-partner:21535 BUG=chrome-os-partner:25990 BRANCH=panther TEST=manual: Boot on Panther and look in /sys/firmware/log for the string "PCIe Root Port 4 ASPM is enabled" Change-Id: I294571c113a8909adb2e97afca92aef9a1af917c Signed-off-by: Stefan Reinauer Signed-off-by: Stefan Reinauer Reviewed-on: https://chromium-review.googlesource.com/187153 Reviewed-by: Duncan Laurie Tested-by: Stefan Reinauer Commit-Queue: Stefan Reinauer Reviewed-on: http://review.coreboot.org/6007 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/mainboard/google/panther/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/mainboard/google/panther') diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb index 9fbe8e62b3..7cc3672f84 100644 --- a/src/mainboard/google/panther/devicetree.cb +++ b/src/mainboard/google/panther/devicetree.cb @@ -61,6 +61,9 @@ chip northbridge/intel/haswell register "sio_i2c0_voltage" = "0" # 3.3V register "sio_i2c1_voltage" = "0" # 3.3V + # Force enable ASPM for PCIe Port 4 + register "pcie_port_force_aspm" = "0x10" + # Enable port coalescing register "pcie_port_coalesce" = "1" -- cgit v1.2.3