From b41ae259d9c1199ae6dc38e37ed21456083750ab Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 4 Jun 2018 17:10:31 -0700 Subject: mb/google/octopus: Enable wake-over-wifi for octopus variants This change enables wake-over-wifi functionality for all octopus variants by making the following changeS: 1. Configure GPIO_119 as SCI active-low 2. Update GPE0_DW1 to include the group that GPIO_119 falls under 3. Add wake property to wifi device BUG=b:77224247 TEST=Verified that wake-over-wifi works on yorp. Change-Id: Ibae199c43e4d96da4c2f68f71a849c2f23d3e7b9 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/26854 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/google/octopus/variants/bip/devicetree.cb | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/mainboard/google/octopus/variants/bip/devicetree.cb') diff --git a/src/mainboard/google/octopus/variants/bip/devicetree.cb b/src/mainboard/google/octopus/variants/bip/devicetree.cb index 7520110ca7..277cb764f0 100644 --- a/src/mainboard/google/octopus/variants/bip/devicetree.cb +++ b/src/mainboard/google/octopus/variants/bip/devicetree.cb @@ -29,7 +29,7 @@ chip soc/intel/apollolake # route, i.e., if this route changes then the affected GPE # offset bits also need to be changed. This sets the PMC register # GPE_CFG fields. - register "gpe0_dw1" = "PMC_GPE_NW_63_32" + register "gpe0_dw1" = "PMC_GPE_N_63_32" register "gpe0_dw2" = "PMC_GPE_N_95_64" register "gpe0_dw3" = "PMC_GPE_NW_31_0" @@ -117,6 +117,7 @@ chip soc/intel/apollolake device pci 12.0 off end # - SATA device pci 13.0 on chip drivers/intel/wifi + register "wake" = "GPE0_DW1_11" device pci 00.0 on end end end # - PCIe-A 0 Onboard M2 Slot(Wifi) -- cgit v1.2.3