From 0be087deee20dee48284e867c378d0ebd1b57940 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sun, 24 Jun 2018 23:00:13 -0700 Subject: mb/google/octopus: Use the newly added override devicetree feature Now that sconfig is able to support variant-specific override trees, this change updates octopus boards to use this feature. Following devices are moved from baseboard devicetree to variant specific devicetree: 1. Touchscreen 2. Trackpad 3. Digitizer 4. Audio codec BUG=b:80081934 TEST=Verified that the right devices show up in static.c for each variant. Change-Id: I8df0cdf4dbcd7613aa4ef4042c272eca2915da9e Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/27219 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- .../google/octopus/variants/bip/devicetree.cb | 222 --------------------- 1 file changed, 222 deletions(-) delete mode 100644 src/mainboard/google/octopus/variants/bip/devicetree.cb (limited to 'src/mainboard/google/octopus/variants/bip/devicetree.cb') diff --git a/src/mainboard/google/octopus/variants/bip/devicetree.cb b/src/mainboard/google/octopus/variants/bip/devicetree.cb deleted file mode 100644 index 8f2992b023..0000000000 --- a/src/mainboard/google/octopus/variants/bip/devicetree.cb +++ /dev/null @@ -1,222 +0,0 @@ -chip soc/intel/apollolake - device cpu_cluster 0 on - device lapic 0 on end - end - - register "pcie_rp_clkreq_pin[2]" = "3" # wifi/bt - # Disable unused clkreq of PCIe root ports - register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" - register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" - register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" - register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" - register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" - - # Set de-emphasis to disabled for PCIE WiFI (Thunderpeak) - # as it is required for detection - register "pcie_rp_deemphasis_enable[2]" = "0" - # Set de-emphasis to default (enabled) for remaining ports - register "pcie_rp_deemphasis_enable[0]" = "1" - register "pcie_rp_deemphasis_enable[1]" = "1" - register "pcie_rp_deemphasis_enable[3]" = "1" - register "pcie_rp_deemphasis_enable[4]" = "1" - register "pcie_rp_deemphasis_enable[5]" = "1" - - # GPIO for PERST_0 (WLAN_PE_RST) - register "prt0_gpio" = "GPIO_164" - - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route, i.e., if this route changes then the affected GPE - # offset bits also need to be changed. This sets the PMC register - # GPE_CFG fields. - # DW1 is used by: - # - GPIO_63 - H1_PCH_INT_ODL - # DW2 is used by: - # - GPIO_141 - EC_PCH_WAKE_ODL - # - GPIO_142 - TRACKPAD_INT2_1V8_ODL - # DW3 is used by: - # - GPIO_117 - LTE_WAKE_ODL - # - GPIO_119 - WLAN_PCIE_WAKE_ODL - register "gpe0_dw1" = "PMC_GPE_NW_63_32" - register "gpe0_dw2" = "PMC_GPE_N_95_64" - register "gpe0_dw3" = "PMC_GPE_N_63_32" - - # PL1 override 8000 mW: Due to error in the energy calculation for - # current VR solution. Experiments show that SoC TDP max (6W) can - # be reached when RAPL PL1 is set to 8W. - register "tdp_pl1_override_mw" = "8000" - # Set RAPL PL2 to 15W. - register "tdp_pl2_override_mw" = "15000" - - # Minimum SLP S3 assertion width 28ms. - register "slp_s3_assertion_width_usecs" = "28000" - - # Enable lpss s0ix - register "lpss_s0ix_enable" = "1" - - # Enable DPTF - register "dptf_enable" = "1" - - # Enable Audio Clock and Power gating - register "hdaudio_clk_gate_enable" = "1" - register "hdaudio_pwr_gate_enable" = "1" - register "hdaudio_bios_config_lockdown" = "1" - - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| GSPI0 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| | before memory is up | - #| I2C0 | Digitizer | - #| I2C5 | Audio | - #| I2C6 | Trackpad | - #| I2C7 | Touchscreen | - #+-------------------+---------------------------+ - register "common_soc_config" = "{ - .gspi[0] = { - .speed_mhz = 1, - .early_init = 1, - }, - .i2c[0] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 152, - .fall_time_ns = 30, - }, - .i2c[5] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 104, - .fall_time_ns = 52, - }, - .i2c[6] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 114, - .fall_time_ns = 164, - .data_hold_time_ns = 350, - }, - .i2c[7] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 76, - .fall_time_ns = 164, - }, - }" - - register "pnp_settings" = "PNP_PERF_POWER" - - device domain 0 on - device pci 00.0 on end # - Host Bridge - device pci 00.1 on end # - DPTF - device pci 00.2 off end # - NPK - device pci 02.0 on end # - Gen - device pci 03.0 on end # - Iunit - device pci 0c.0 on end # - CNVi - device pci 0d.0 on end # - P2SB - device pci 0d.1 on end # - PMC - device pci 0d.2 on end # - Fast SPI - device pci 0d.3 on end # - Shared SRAM - device pci 0e.0 on - chip drivers/generic/max98357a - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_91)" - register "sdmode_delay" = "5" - device generic 0 on end - end - end # - Audio - device pci 0f.0 on end # - Heci1 - device pci 0f.1 on end # - Heci2 - device pci 0f.2 on end # - Heci3 - device pci 11.0 off end # - ISH - device pci 12.0 off end # - SATA - device pci 13.0 on - chip drivers/intel/wifi - register "wake" = "GPE0_DW3_11" - device pci 00.0 on end - end - end # - PCIe-A 0 Onboard M2 Slot(Wifi) - device pci 13.1 off end # - PCIe-A 1 - device pci 13.2 off end # - PCIe-A 2 - device pci 13.3 off end # - PCIe-A 3 - device pci 14.0 off end # - PCIe-B 0 - device pci 14.1 off end # - PCIe-B 1 - device pci 15.0 on end # - XHCI - device pci 15.1 off end # - XDCI - device pci 16.0 on - chip drivers/i2c/hid - register "generic.hid" = ""WCOM50C1"" - register "generic.desc" = ""WCOM Digitizer"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_139_IRQ)" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" - register "generic.has_power_resource" = "1" - register "hid_desc_reg_offset" = "0x1" - device i2c 0x9 on end - end - end # - I2C 0 - device pci 16.1 on end # - I2C 1 - device pci 16.2 on end # - I2C 2 - device pci 16.3 on end # - I2C 3 - device pci 17.0 on end # - I2C 4 - device pci 17.1 on - chip drivers/i2c/generic - register "hid" = ""10EC5682"" - register "name" = ""RT58"" - register "desc" = ""Realtek RT5682"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)" - register "probed" = "1" - register "property_count" = "1" - # Set the jd_src to RT5668_JD1 for jack detection - register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" - register "property_list[0].name" = ""realtek,jd-src"" - register "property_list[0].integer" = "1" - device i2c 1a on end - end - end # - I2C 5 - device pci 17.2 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_135_IRQ)" - register "wake" = "GPE0_DW2_02" - register "probed" = "1" - device i2c 15 on end - end - end # - I2C 6 - device pci 17.3 on - chip drivers/i2c/generic - register "hid" = ""ELAN0001"" - register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" - register "probed" = "1" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" - register "reset_delay_ms" = "20" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_213)" - register "enable_delay_ms" = "1" - register "has_power_resource" = "1" - device i2c 10 on end - end - end # - I2C 7 - device pci 18.0 on end # - UART 0 - device pci 18.1 off end # - UART 1 - device pci 18.2 on end # - UART 2 - device pci 18.3 off end # - UART 3 - device pci 19.0 on - chip drivers/spi/acpi - register "hid" = "ACPI_DT_NAMESPACE_HID" - register "compat_string" = ""google,cr50"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_63_IRQ)" - device spi 0 on end - end - end # - GSPI 0 - device pci 19.1 off end # - SPI 1 - device pci 19.2 on end # - SPI 2 - device pci 1a.0 on end # - PWM - device pci 1c.0 on end # - eMMC - device pci 1e.0 off end # - SDIO - device pci 1f.0 on - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # - ESPI - device pci 1f.1 on end # - SMBUS - end -end -- cgit v1.2.3