From 5e83e8b130a7072fd62b581f260545689dcf73fc Mon Sep 17 00:00:00 2001
From: Hannah Williams <hannah.williams@intel.com>
Date: Fri, 9 Feb 2018 18:35:17 -0800
Subject: mb/google/octopus: Add new board

Add octopus board using GLK soc. Copied base code from mainboard/intel/glkrvp.
TODO: Fix as per octopus schematic.

Change-Id: Ic8c25b3fafbfef31b8b3b802acb3bc53ee7146b6
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/23685
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/octopus/ec.c | 62 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 62 insertions(+)
 create mode 100644 src/mainboard/google/octopus/ec.c

(limited to 'src/mainboard/google/octopus/ec.c')

diff --git a/src/mainboard/google/octopus/ec.c b/src/mainboard/google/octopus/ec.c
new file mode 100644
index 0000000000..8ed862c7bc
--- /dev/null
+++ b/src/mainboard/google/octopus/ec.c
@@ -0,0 +1,62 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec.h>
+#include <intelblocks/lpc_lib.h>
+#include <rules.h>
+#include <variant/ec.h>
+
+static void ramstage_ec_init(void)
+{
+	static const struct google_chromeec_event_info info = {
+		.log_events = MAINBOARD_EC_LOG_EVENTS,
+		.sci_events = MAINBOARD_EC_SCI_EVENTS,
+		.s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
+		.s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
+		.s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS,
+	};
+
+	printk(BIOS_ERR, "mainboard: EC init\n");
+
+	google_chromeec_events_init(&info, acpi_is_wakeup_s3());
+}
+
+static void bootblock_ec_init(void)
+{
+	uint16_t ec_ioport_base;
+	size_t ec_ioport_size;
+
+	/*
+	 * Set up LPC decoding for the ChromeEC I/O port ranges:
+	 * - Ports 62/66, 60/64, and 200->208
+	 * - ChromeEC specific communication I/O ports.
+	 */
+	lpc_enable_fixed_io_ranges(LPC_IOE_EC_62_66 | LPC_IOE_KBC_60_64
+		| LPC_IOE_LGE_200);
+	google_chromeec_ioport_range(&ec_ioport_base, &ec_ioport_size);
+	lpc_open_pmio_window(ec_ioport_base, ec_ioport_size);
+}
+
+void mainboard_ec_init(void)
+{
+	if (ENV_RAMSTAGE)
+		ramstage_ec_init();
+	else if (ENV_BOOTBLOCK)
+		bootblock_ec_init();
+}
-- 
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