From c77259c4e5e02fcf829afe9bf437b70dbddcbf3c Mon Sep 17 00:00:00 2001 From: Vadim Bendebury Date: Tue, 14 Feb 2017 10:48:11 +0800 Subject: google/oak: Support cr50 over I2C on rowan This patch enables TPM2 using cr50 over I2C for the Rowan board, and adds an mt8173 specific TPM IRQ polling function. The function relies on the appropriate EINT input configured to trigger the ready status on the rising edge. The cr50 TPM is on I2C address 0x50. The cr50 interrupt GPIO is also made available for use by depthcharge via the coreboot tables. BRANCH=none BUG=b:36786804 TEST=Boot rowan w/ serial enabled, verify coreboot and depthcharge are configured to use IRQ flow control when talking to the Cr50 TPM. Change-Id: If6cdd0e39e4ac86538f27f322c55c329179ee084 Signed-off-by: Vadim Bendebury Signed-off-by: Daniel Kurtz Reviewed-on: https://review.coreboot.org/19364 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/mainboard/google/oak/gpio.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mainboard/google/oak/gpio.h') diff --git a/src/mainboard/google/oak/gpio.h b/src/mainboard/google/oak/gpio.h index 3c0f51afb6..35f47c6b6e 100644 --- a/src/mainboard/google/oak/gpio.h +++ b/src/mainboard/google/oak/gpio.h @@ -42,6 +42,8 @@ enum { EC_IN_RW = PAD_DAIPCMIN, /* EC AP suspend */ EC_SUSPEND_L = PAD_KPROW1, + /* Cr50 interrupt */ + CR50_IRQ = PAD_EINT16, }; void setup_chromeos_gpios(void); -- cgit v1.2.3