From efddcfbb52cd328ad2eb86d88cd306ac30294109 Mon Sep 17 00:00:00 2001 From: Daisuke Nojiri Date: Thu, 4 Sep 2014 09:55:34 -0700 Subject: vboot2: separate verstage from bootblock With CONFIG_RETURN_FROM_VERSTAGE false, the verstage loads the romstage over the bootblock, then exits to the romstage. this is necessary for some SOC (e.g. tegra124) which runs the bootblock on a different architecture. With CONFIG_RETURN_FROM_VERSTAGE true, the verstage returns to the bootblock. Then, the bootblock loads the romstage over the verstage and exits to the romstage. this is probably necessary for some SOC (e.g. rockchip) which does not have SRAM big enough to fit the verstage and the romstage at the same time. BUG=none TEST=Built Blaze with USE=+/-vboot2. Ran faft on Blaze. BRANCH=none Original-Signed-off-by: Daisuke Nojiri Original-Change-Id: I673945c5e21afc800d523fbb25d49fdc83693544 Original-Reviewed-on: https://chromium-review.googlesource.com/212365 Original-Reviewed-by: Aaron Durbin Note: This purposefully is probably broken in vendorcode/google/chromeos as I'm just trying to set a base for dropping more patches in. The vboot paths will have to change from how they are currently constructed. (cherry picked from commit 4fa17395113d86445660091413ecb005485f8014) Signed-off-by: Aaron Durbin Change-Id: I9117434ce99695f9b7021a06196d864f180df5c9 Reviewed-on: http://review.coreboot.org/8881 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/mainboard/google/nyan_big/romstage.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src/mainboard/google/nyan_big') diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c index 0baf2b74f8..fffe0de282 100644 --- a/src/mainboard/google/nyan_big/romstage.c +++ b/src/mainboard/google/nyan_big/romstage.c @@ -46,8 +46,6 @@ static void __attribute__((noinline)) romstage(void) timestamp_init(0); timestamp_add_now(TS_START_ROMSTAGE); - configure_l2_cache(); - console_init(); exception_init(); @@ -58,6 +56,7 @@ static void __attribute__((noinline)) romstage(void) u32 dram_end = sdram_max_addressable_mb(); /* plus one... */ u32 dram_size = dram_end - dram_start; + configure_l2_cache(); mmu_init(); /* Device memory below DRAM is uncached. */ mmu_config_range(0, dram_start, DCACHE_OFF); -- cgit v1.2.3