From 5a056d30a1fd609994e0a9aa70f5788c68e3a785 Mon Sep 17 00:00:00 2001 From: Ken Chang Date: Tue, 22 Apr 2014 12:55:00 +0800 Subject: tegra124: modify panel init sequence Panel datasheet defines some delay between PWM signal out and backlight enable. This change fixes the current sequence and makes the delays adjustable by dt setting. BRANCH=none BUG=chrome-os-partner:28008 TEST=Verified on Big DVT and Nyan/Norrin panels. Panel works fine with dev mode, and the measurement of power on sequence meets panel requirements. Original-Change-Id: If6015bbb6015a3b203d425f5e90f676ad786b5e8 Original-Signed-off-by: Ken Chang Original-Reviewed-on: https://chromium-review.googlesource.com/196183 Original-Reviewed-by: Hung-Te Lin (cherry picked from commit 2bbcaa7281222ffc0b4026e8b1eb4c210a8e308a) Signed-off-by: Marc Jones Change-Id: Id6424f66eb8dc6adeb70eaa33df742f4e57983c3 Reviewed-on: http://review.coreboot.org/7776 Reviewed-by: Stefan Reinauer Tested-by: build bot (Jenkins) --- src/mainboard/google/nyan/devicetree.cb | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard/google/nyan/devicetree.cb') diff --git a/src/mainboard/google/nyan/devicetree.cb b/src/mainboard/google/nyan/devicetree.cb index 885445022e..e7ae54d52b 100644 --- a/src/mainboard/google/nyan/devicetree.cb +++ b/src/mainboard/google/nyan/devicetree.cb @@ -47,6 +47,7 @@ chip soc/nvidia/tegra124 # various panel delay time register "vdd_delay_ms" = "200" + register "pwm_to_bl_delay_ms" = "10" register "vdd_to_hpd_delay_ms" = "200" register "hpd_unplug_min_us" = "2000" register "hpd_plug_min_us" = "250" -- cgit v1.2.3