From 8af6b57788a0066a8b0d6264ae234e4131eefbd7 Mon Sep 17 00:00:00 2001
From: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Date: Thu, 8 Apr 2021 11:48:30 +0800
Subject: mb/google/mancomb: Add initial I2C configuration

BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I483c2e77eedcb434709b67bf9b3fbca636499508
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
---
 .../google/mancomb/variants/baseboard/devicetree.cb |  3 +++
 .../google/mancomb/variants/mancomb/overridetree.cb | 21 +++++++++++++++++++++
 2 files changed, 24 insertions(+)

(limited to 'src/mainboard/google/mancomb/variants')

diff --git a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb
index b368574f68..533e2b4faa 100644
--- a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb
@@ -38,6 +38,9 @@ chip soc/amd/cezanne
 		.vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1) | ESPI_VW_IRQ_LEVEL_HIGH(12),
 	}"
 
+	register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL |
+					GPIO_I2C2_SCL | GPIO_I2C3_SCL"
+
 	device domain 0 on
 		device ref gpp_bridge_0 on end # WLAN
 		device ref gpp_bridge_1 on end # SD
diff --git a/src/mainboard/google/mancomb/variants/mancomb/overridetree.cb b/src/mainboard/google/mancomb/variants/mancomb/overridetree.cb
index eae9425bf7..59fe79046c 100644
--- a/src/mainboard/google/mancomb/variants/mancomb/overridetree.cb
+++ b/src/mainboard/google/mancomb/variants/mancomb/overridetree.cb
@@ -1,4 +1,25 @@
 chip soc/amd/cezanne
 	device domain 0 on
 	end # domain
+
+	# I2C Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| I2C0              | memory SPD bus            |
+	#| I2C2              | Codec			 |
+	#| I2C3              | H1/D2 TPM                 |
+	#+-------------------+---------------------------+
+	register "i2c[0]" = "{
+		.speed = I2C_SPEED_FAST,
+		.early_init = true,
+	}"
+	register "i2c[2]" = "{
+		.speed = I2C_SPEED_FAST,
+	}"
+	register "i2c[3]" = "{
+		.speed = I2C_SPEED_FAST,
+		.early_init = true,
+	}"
+
 end # chip soc/amd/cezanne
-- 
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