From ffbb3c0b8abea621eb7a1583d630cf06c8cbfbbc Mon Sep 17 00:00:00 2001 From: Vladimir Serbinenko Date: Wed, 10 Feb 2016 01:36:25 +0100 Subject: Merge sandy/ivybridge romstage flow for MRC and non-MRC. Change-Id: I11e09804ed1d8a7ae8b8d4502bd18f6be933f9fa Signed-off-by: Vladimir Serbinenko Reviewed-on: https://review.coreboot.org/13656 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc Reviewed-by: Martin Roth --- src/mainboard/google/link/gpio.h | 2 +- src/mainboard/google/link/romstage.c | 103 ++++++----------------------------- 2 files changed, 18 insertions(+), 87 deletions(-) (limited to 'src/mainboard/google/link') diff --git a/src/mainboard/google/link/gpio.h b/src/mainboard/google/link/gpio.h index 1dab97e75e..ea6110e8f9 100644 --- a/src/mainboard/google/link/gpio.h +++ b/src/mainboard/google/link/gpio.h @@ -98,7 +98,7 @@ const struct pch_gpio_set3 pch_gpio_set3_direction = { const struct pch_gpio_set3 pch_gpio_set3_level = { }; -const struct pch_gpio_map link_gpio_map = { +const struct pch_gpio_map mainboard_gpio_map = { .set1 = { .mode = &pch_gpio_set1_mode, .direction = &pch_gpio_set1_direction, diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index a0970df562..2f40ba5186 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -33,7 +33,6 @@ #include #include "ec/google/chromeec/ec.h" #include -#include #include #include #include "gpio.h" @@ -42,7 +41,7 @@ #include -static void pch_enable_lpc(void) +void pch_enable_lpc(void) { const struct device *lpc; const struct southbridge_intel_bd82x6x_config *config = NULL; @@ -68,7 +67,7 @@ static void pch_enable_lpc(void) pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec); } -static void rcba_config(void) +void rcba_config(void) { u32 reg32; @@ -144,13 +143,9 @@ static void copy_spd(struct pei_data *peid) sizeof(peid->spd_data[0])); } -#include -void main(unsigned long bist) +void mainboard_fill_pei_data(struct pei_data *pei_data) { - int boot_mode = 0; - int cbmem_was_initted; - - struct pei_data pei_data = { + struct pei_data pei_data_template = { .pei_version = PEI_VERSION, .mchbar = (uintptr_t)DEFAULT_MCHBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR, @@ -195,89 +190,25 @@ void main(unsigned long bist) { 0, 4, 0x0000 }, /* P13: Empty */ }, }; + *pei_data = pei_data_template; + copy_spd(pei_data); +} - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - - if (bist == 0) - enable_lapic(); - - pch_enable_lpc(); - - /* Enable GPIOs */ - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); - pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); - setup_pch_gpios(&link_gpio_map); - - /* Initialize console device(s) */ - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected\n"); - boot_mode = 1; - - /* System is not happy after keyboard reset... */ - printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); - outb(0x6, 0xcf9); - halt(); - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - sandybridge_early_initialization(SANDYBRIDGE_MOBILE); - printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); - - boot_mode = southbridge_detect_s3_resume() ? 2 : 0; - if (boot_mode == 0) { +void mainboard_early_init(int s3resume) +{ + if (!s3resume) { /* This is the fastest way to let users know * the Intel CPU is now alive. */ google_chromeec_kbbacklight(100); } +} - post_code(0x38); - /* Enable SPD ROMs and DDR-III DRAM */ - enable_smbus(); - - /* Prepare USB controller early in S3 resume */ - if (boot_mode == 2) - enable_usb_bar(); - - post_code(0x39); - - copy_spd(&pei_data); - - post_code(0x3a); - pei_data.boot_mode = boot_mode; - timestamp_add_now(TS_BEFORE_INITRAM); - sdram_initialize(&pei_data); - - timestamp_add_now(TS_AFTER_INITRAM); - post_code(0x3c); - - rcba_config(); - post_code(0x3d); - - quick_ram_check(); - post_code(0x3e); - - cbmem_was_initted = !cbmem_recovery(boot_mode==2); - if (boot_mode!=2) - save_mrc_data(&pei_data); - - if (boot_mode==2 && !cbmem_was_initted) { - /* Failed S3 resume, reset to come up cleanly */ - outb(0x6, 0xcf9); - halt(); - } - northbridge_romstage_finalize(boot_mode==2); +int mainboard_should_reset_usb(int s3resume) +{ + return !s3resume; +} - post_code(0x3f); - if (CONFIG_LPC_TPM) { - init_tpm(boot_mode == 2); - } +void mainboard_config_superio(void) +{ } -- cgit v1.2.3