From 3e5c12691f217477cbf30bdbfb651d2d7da9142f Mon Sep 17 00:00:00 2001 From: david Date: Mon, 4 Jan 2016 14:16:47 +0800 Subject: google/lars: Enable eMMC HS400 mode Kingston eMMC can now run under HS400 mode. BUG=chrome-os-partner:48017 BRANCH=none TEST=run consecutive boot 100 times on Lars proto Kingston SKU, and MMC errors didn't happen. Change-Id: I3c16db6111273fbbabbfba1c315edc780fe23525 Signed-off-by: Patrick Georgi Original-Commit-Id: ac474bd7bd33f11904a27691e9eb61bdaf212c6b Original-Change-Id: I9e47b6ba64ac94acff7673fca86fa62bfb30edd9 Original-Signed-off-by: David Wu Original-Reviewed-on: https://chromium-review.googlesource.com/320194 Original-Commit-Ready: David Wu Original-Tested-by: David Wu Original-Reviewed-by: Aaron Durbin Original-Reviewed-by: Subrata Banik Reviewed-on: https://review.coreboot.org/13004 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/mainboard/google/lars/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/google/lars') diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb index 689babb5a5..e858eeac74 100644 --- a/src/mainboard/google/lars/devicetree.cb +++ b/src/mainboard/google/lars/devicetree.cb @@ -24,7 +24,7 @@ chip soc/intel/skylake register "IoBufferOwnership" = "3" register "SmbusEnable" = "1" register "ScsEmmcEnabled" = "1" - register "ScsEmmcHs400Enabled" = "0" + register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "0" register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" -- cgit v1.2.3