From d1aa8eba72c640e94ef410bbb0f37c35ee8c9a5c Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Fri, 5 Oct 2018 18:45:15 -0600 Subject: amd/stoneyridge: Rename GppClkCntrl fields Make the field names of the MISCx00 GPPClkCntrl more manageable by shortening their names. Make the definitions look more like the rest of the header file. Change-Id: I515cd664808e38851a7dbdba899df4fb9bbbcde6 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/29014 Tested-by: build bot (Jenkins) Reviewed-by: Richard Spiegel --- src/mainboard/google/kahlee/mainboard.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'src/mainboard/google/kahlee') diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index bfd1f2f649..ebdcc935e9 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -146,15 +146,15 @@ static void mainboard_init(void *chip_info) /* Set low-power mode for BayHub eMMC bridge's PCIe clock. */ clrsetbits_le32((uint32_t *)(MISC_MMIO_BASE + GPP_CLK_CNTRL), - GPP_CLK2_CLOCK_REQ_MAP_MASK, - GPP_CLK2_CLOCK_REQ_MAP_CLK_REQ2 << - GPP_CLK2_CLOCK_REQ_MAP_SHIFT); + GPP_CLK2_REQ_MAP_MASK, + GPP_CLK2_REQ_MAP_CLK_REQ2 << + GPP_CLK2_REQ_MAP_SHIFT); /* Same for the WiFi */ clrsetbits_le32((uint32_t *)(MISC_MMIO_BASE + GPP_CLK_CNTRL), - GPP_CLK0_CLOCK_REQ_MAP_MASK, - GPP_CLK0_CLOCK_REQ_MAP_CLK_REQ0 << - GPP_CLK0_CLOCK_REQ_MAP_SHIFT); + GPP_CLK0_REQ_MAP_MASK, + GPP_CLK0_REQ_MAP_CLK_REQ0 << + GPP_CLK0_REQ_MAP_SHIFT); } /************************************************* -- cgit v1.2.3