From 95afc463824db373333ac80656b00d7ee05eaa4f Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Tue, 7 Nov 2017 14:08:02 -0700 Subject: mainboard/google/kahlee: Define MEM_CONFIG3 for Kahlee variant Even though this GPIO isn't used for Kahlee, it needs to be defined so that the weak version of the variant_board_id() function can compile. BUG=b:68293392 TEST=Build and boot kahlee Change-Id: Ia8daf70fbafe02ec37c6b5eb8421cdb11de3be8b Signed-off-by: Martin Roth Reviewed-on: https://review.coreboot.org/22371 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/mainboard/google/kahlee') diff --git a/src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h b/src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h index dfb6354a3e..28643fb08a 100644 --- a/src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h +++ b/src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h @@ -22,6 +22,12 @@ #define MEM_CONFIG0 GPIO_135 #define MEM_CONFIG1 GPIO_140 #define MEM_CONFIG2 GPIO_144 +/* + * Kahlee only uses 3 GPIOs to determine memory configuration, but other + * variants use 4. MEM_CONFIG3 must be defined so that the weak baseboard + * version of the variant_board_id() function can compile. + */ +#define MEM_CONFIG3 0 /* SPI Write protect */ #define CROS_WP_GPIO GPIO_142 -- cgit v1.2.3