From 6985a7b7d6367b4aae3f5c03290f19feea7580f0 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Thu, 7 Jun 2018 09:00:22 -0600 Subject: mainboard/google/kahlee: Use 66MHz SPI clock for fast read Looking at the 100MHz signal, we were violating the timing requirements. 66MHz still isn't great, but it's a good tradeoff between improving the signal and losing boot speed time. This slows down the boot time by about 20mS. BUG=b:109583457 TEST=Boot grunt, look at signal on scope Change-Id: I7ce70c992822dd17c5877226e74c1890660768c6 Signed-off-by: Martin Roth Reviewed-on: https://review.coreboot.org/26950 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/mainboard/google/kahlee/bootblock/bootblock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/google/kahlee') diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c index 8f124b36ff..7e6524d1d5 100644 --- a/src/mainboard/google/kahlee/bootblock/bootblock.c +++ b/src/mainboard/google/kahlee/bootblock/bootblock.c @@ -44,7 +44,7 @@ void bootblock_mainboard_init(void) /* Set SPI speeds before verstage. Needed for TPM */ sb_set_spi100(SPI_SPEED_33M, /* Normal */ - SPI_SPEED_100M, /* Fast */ + SPI_SPEED_66M, /* Fast */ SPI_SPEED_66M, /* AltIO */ SPI_SPEED_66M); /* TPM */ -- cgit v1.2.3