From 55009af42c39f413c49503670ce9bc2858974962 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 2 Dec 2019 22:03:27 -0800 Subject: Change all clrsetbits_leXX() to clrsetbitsXX() This patch changes all existing instances of clrsetbits_leXX() to the new endian-independent clrsetbitsXX(), after double-checking that they're all in SoC-specific code operating on CPU registers and not actually trying to make an endian conversion. This patch was created by running sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g' across the codebase and cleaning up formatting a bit. Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin --- src/mainboard/google/kahlee/mainboard.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'src/mainboard/google/kahlee') diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index f218f3f31b..0173064b10 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -147,16 +147,16 @@ static void mainboard_init(void *chip_info) pm_write8(PM_PCIB_CFG, pm_read8(PM_PCIB_CFG) | PM_GENINT_DISABLE); /* Set low-power mode for BayHub eMMC bridge's PCIe clock. */ - clrsetbits_le32((uint32_t *)(ACPIMMIO_MISC_BASE + GPP_CLK_CNTRL), - GPP_CLK2_REQ_MAP_MASK, - GPP_CLK2_REQ_MAP_CLK_REQ2 << - GPP_CLK2_REQ_MAP_SHIFT); + clrsetbits32((uint32_t *)(ACPIMMIO_MISC_BASE + GPP_CLK_CNTRL), + GPP_CLK2_REQ_MAP_MASK, + GPP_CLK2_REQ_MAP_CLK_REQ2 << + GPP_CLK2_REQ_MAP_SHIFT); /* Same for the WiFi */ - clrsetbits_le32((uint32_t *)(ACPIMMIO_MISC_BASE + GPP_CLK_CNTRL), - GPP_CLK0_REQ_MAP_MASK, - GPP_CLK0_REQ_MAP_CLK_REQ0 << - GPP_CLK0_REQ_MAP_SHIFT); + clrsetbits32((uint32_t *)(ACPIMMIO_MISC_BASE + GPP_CLK_CNTRL), + GPP_CLK0_REQ_MAP_MASK, + GPP_CLK0_REQ_MAP_CLK_REQ0 << + GPP_CLK0_REQ_MAP_SHIFT); } /************************************************* -- cgit v1.2.3