From 97ab880082505b4aa0d4b2a058e850bd3376d9b8 Mon Sep 17 00:00:00 2001 From: Chris Ching Date: Tue, 6 Feb 2018 10:28:49 -0700 Subject: mainboard/google/kahlee: Add tis_plat_irq_status For variants that have a cr50 tpm, this enables faster polling when interacting with the tpm. BUG=b:72838769 BRANCH=none TEST=verified on grunt that irq is used and not timeouts for tpm Change-Id: I5786d334b6c1cc70f4c7107c75b07a7e27ac4428 Signed-off-by: Chris Ching Signed-off-by: Martin Roth Reviewed-on: https://review.coreboot.org/23626 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/google/kahlee/variants/baseboard/Makefile.inc | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'src/mainboard/google/kahlee/variants/baseboard/Makefile.inc') diff --git a/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc b/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc index fcaf365830..c4c2f9da26 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2017 Google, Inc. +# Copyright (C) 2018 Google, LLC. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -16,7 +16,11 @@ bootblock-y += gpio.c bootblock-y += OemCustomize.c +verstage-y += tpm_tis.c + romstage-y += gpio.c romstage-y += memory.c +romstage-y += tpm_tis.c ramstage-y += gpio.c +ramstage-y += tpm_tis.c -- cgit v1.2.3