From 2983c708155466d88776338b3a7faec9f80f0134 Mon Sep 17 00:00:00 2001 From: Richard Spiegel Date: Mon, 20 Nov 2017 12:30:32 -0700 Subject: Create SOC description file soc.asl Request from commit 519680948b (move carrizo_fch.asl code to soc), merge several includes into a single file in soc directory. Rename soc_fch.asl to sb_fch.asl. Rename fch.asl to sb_pci0_fch.asl. Then copy the required section from dsdt.asl into a new soc.asl. Affected boards: amd/gardenia and google/kahlee. BUG=b:69368752 Change-Id: I83d850cf9457f7c2c787336823d993ae2e9d28ce Signed-off-by: Richard Spiegel Reviewed-on: https://review.coreboot.org/22541 Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- src/mainboard/google/kahlee/dsdt.asl | 17 +++-------------- 1 file changed, 3 insertions(+), 14 deletions(-) (limited to 'src/mainboard/google/kahlee/dsdt.asl') diff --git a/src/mainboard/google/kahlee/dsdt.asl b/src/mainboard/google/kahlee/dsdt.asl index 885dd8dce0..ded0dc8779 100644 --- a/src/mainboard/google/kahlee/dsdt.asl +++ b/src/mainboard/google/kahlee/dsdt.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2015-2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -61,19 +61,8 @@ DefinitionBlock ( Name(_UID, 0xAA) } - Device(PCI0) { - /* Describe the AMD Northbridge */ - #include - - /* Describe the AMD Fusion Controller Hub Southbridge */ - #include - } - - /* Describe PCI INT[A-H] for the Southbridge */ - #include - - /* Describe the devices in the Southbridge */ - #include + /* Describe the SOC */ + #include } /* End \_SB scope */ -- cgit v1.2.3