From 73cd7cf0f28d77a9a4afe56ca0e0a9485b2eae48 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Sun, 8 Apr 2018 15:05:12 +0200 Subject: src/amd/stoneyridge: Fix a typo (EDGEL_TRIG -> EDGE_TRIG) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixes: 2269a3c328 ("soc/amd/stoneyridge: Add functions for GPIO interrupts") Change-Id: I5730259bc6819defc482d31644e1f476679257b2 Signed-off-by: Jonathan Neuschäfer Reviewed-on: https://review.coreboot.org/25588 Reviewed-by: Martin Roth Reviewed-by: Chris Ching Reviewed-by: Paul Menzel Reviewed-by: Justin TerAvest Tested-by: build bot (Jenkins) --- src/mainboard/google/kahlee/bootblock/bootblock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/google/kahlee/bootblock') diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c index 1eb18f1667..641287c1bd 100644 --- a/src/mainboard/google/kahlee/bootblock/bootblock.c +++ b/src/mainboard/google/kahlee/bootblock/bootblock.c @@ -39,7 +39,7 @@ void bootblock_mainboard_init(void) /* Configure cr50 interrupt pin for use in polling tpm status */ if (IS_ENABLED(CONFIG_MAINBOARD_HAS_TPM_CR50)) { - const uint32_t flags = GPIO_EDGEL_TRIG | GPIO_ACTIVE_LOW | + const uint32_t flags = GPIO_EDGE_TRIG | GPIO_ACTIVE_LOW | GPIO_INT_STATUS_EN; gpio_set_interrupt(H1_PCH_INT, flags); } -- cgit v1.2.3