From 76118a7d192af29f26fa0dbe85b1cd324cb774d5 Mon Sep 17 00:00:00 2001 From: chris wang Date: Thu, 18 Oct 2018 18:52:58 +0800 Subject: mb/google/kahlee: Enable 2T mode for liara Liara auto restart issue is caused by memory access error and consequent kernel panic. To solve this issue, revert the CL:1243666 (Disable NbP-state on Liara) and use 2T mode instead. BUG=b:116082728 TEST=verify the 2T mode is enabled/boot into ChromeOS and no auto restart/run memtester passed 10 cycle. Change-Id: I3a96276d88ffb70530d72b15c07b59a01cc6209a Signed-off-by: Chris Wang Reviewed-on: https://review.coreboot.org/29179 Tested-by: build bot (Jenkins) Reviewed-by: Richard Spiegel --- src/mainboard/google/kahlee/OemCustomize.c | 27 ++++++++++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-) (limited to 'src/mainboard/google/kahlee/OemCustomize.c') diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c index d78f7846e5..a0bd8cddbd 100644 --- a/src/mainboard/google/kahlee/OemCustomize.c +++ b/src/mainboard/google/kahlee/OemCustomize.c @@ -15,6 +15,7 @@ #include #include +#include #define DIMMS_PER_CHANNEL 1 #if DIMMS_PER_CHANNEL > MAX_DIMMS_PER_CH @@ -34,12 +35,32 @@ static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), PSO_END }; +/* TODO: Remove when no longer needed */ +static const PSO_ENTRY DDR4LiaraMemoryConfiguration[] = { + DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY), + NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, DIMMS_PER_CHANNEL), + NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, MAX_DRAM_CH), + MOTHER_BOARD_LAYERS(LAYERS_6), + MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, + 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), + CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff), + ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff), + CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, + 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), + TBLDRV_CONFIG_TO_OVERRIDE(DIMMS_PER_CHANNEL, ANY_SPEED, VOLT_ANY_, + ANY_), + TBLDRV_CONFIG_ENTRY_SLOWACCMODE(1), + PSO_END +}; void OemPostParams(AMD_POST_PARAMS *PostParams) { - PostParams->MemConfig.PlatformMemoryConfiguration = - (PSO_ENTRY *)DDR4PlatformMemoryConfiguration; - + if ((IS_ENABLED(CONFIG_BOARD_GOOGLE_LIARA)) && (board_id() <= 4)) + PostParams->MemConfig.PlatformMemoryConfiguration = + (PSO_ENTRY *)DDR4LiaraMemoryConfiguration; + else + PostParams->MemConfig.PlatformMemoryConfiguration = + (PSO_ENTRY *)DDR4PlatformMemoryConfiguration; /* * Bank interleaving is enabled by default in AGESA. However, from AMD's * explanation, bank interleaving is really chip select interleave, -- cgit v1.2.3