From 4d56a0625516ba436903d59d9c0a4a13827d89be Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 22 Dec 2018 16:11:52 +0100 Subject: nb/intel/broadwell: Add an option for where verstage starts Previously broadwell used a romcc bootblock and starting verstage in romstage was madatory but with C_ENVIRONMENT_BOOTBLOCK it is also possible to have a separate verstage. This selects using a separate verstage by default but still keeps the option around to use verstage in romstage. With a separate verstage the romstage becomes an RW stage. The mrc.bin however is only added to the RO COREBOOT fmap region as it requires to be run at a specific offset. This means that coreboot will have to jump from a RW region to the RO region for that binary and back to that RW region after that binary is done initializing the memory. Change-Id: I900233cadb3c76da329fb98f93917570e633365f Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/30384 Reviewed-by: Nico Huber Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) --- src/mainboard/google/jecht/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard/google/jecht/Makefile.inc') diff --git a/src/mainboard/google/jecht/Makefile.inc b/src/mainboard/google/jecht/Makefile.inc index 39e9b339e8..28a284e759 100644 --- a/src/mainboard/google/jecht/Makefile.inc +++ b/src/mainboard/google/jecht/Makefile.inc @@ -16,6 +16,7 @@ subdirs-y += spd romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c +verstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += lan.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c led.c -- cgit v1.2.3