From a04072c91743eed03574c6b3e42bdf450b136009 Mon Sep 17 00:00:00 2001 From: Matt Ziegelbaum Date: Tue, 17 Nov 2020 17:20:04 -0500 Subject: mb/google/hatch/var/ambassador: configure FSP option PcieRpSlotImplemented Ambassador is similar to puff. This change matches the PcieRpSlotImplemented configuration with Puff's, originally made for Puff in https://review.coreboot.org/c/coreboot/+/39986. Signed-off-by: Matt Ziegelbaum Change-Id: I5b6246f58c10e03a0d02278ad3621ded39bb6d6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/47685 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/hatch/variants/ambassador/overridetree.cb | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src/mainboard/google/hatch') diff --git a/src/mainboard/google/hatch/variants/ambassador/overridetree.cb b/src/mainboard/google/hatch/variants/ambassador/overridetree.cb index 7b4615320f..7cc920d7ee 100644 --- a/src/mainboard/google/hatch/variants/ambassador/overridetree.cb +++ b/src/mainboard/google/hatch/variants/ambassador/overridetree.cb @@ -402,8 +402,11 @@ chip soc/intel/cannonlake register "device_index" = "0" device pci 00.0 on end end + register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC - device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) + device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) + register "PcieRpSlotImplemented[10]" = "1" + end device pci 1e.3 off end # GSPI #1 end -- cgit v1.2.3