From 43bb6554a24e1dd9944a7d3f518e4374f9e0be79 Mon Sep 17 00:00:00 2001 From: Rizwan Qureshi Date: Wed, 10 Apr 2019 16:58:07 +0530 Subject: mb/google/hatch: Update sleep signal assertion widths Based on the power rail discharge times measured on hatch, update the assertions widths that have to be programmed in SoC. BUG=b:129328209 TEST=warm/cold reboot and S3 are working fine on hatch. Change-Id: I3c6dce0a942e6dcd9e55ef5e58a7e9e8d2b0a1e3 Signed-off-by: Rizwan Qureshi Reviewed-on: https://review.coreboot.org/c/coreboot/+/32266 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/mainboard/google/hatch') diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 7dd41a2a3a..e39f140588 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -47,6 +47,11 @@ chip soc/intel/cannonlake # Unlock GPIO pads register "PchUnlockGpioPads" = "1" + register "PchPmSlpS3MinAssert" = "2" # 50ms + register "PchPmSlpS4MinAssert" = "1" # 1s + register "PchPmSlpSusMinAssert" = "1" # 500ms + register "PchPmSlpAMinAssert" = "3" # 2s + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 register "usb2_ports[2]" = "USB2_PORT_SHORT(OC3)" # Type-A Port 0 -- cgit v1.2.3