From 38f7db79b59dcc45b353e1c28943588309ac9571 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Thu, 23 Jan 2020 10:45:00 +1100 Subject: mainboard/google/hatch: Fix Puff _PR to toggle NIC ISOLATE# for S0ix Turns out when going into S0ix we want the kernel to toggle de-assert to 0 for the ISOLATE# pin on the NIC for S0ix not to be woken by PCIe traffic on PCH. Upon resume the ISOLATE# pin on the NIC is then re-asserted for it to become lively again. BUG=b:147026979 BRANCH=none TEST=Boot puff and do 1500 cycles of S0ix. Change-Id: I3470e1edd93b461b66fc6444541a64339bcdcce3 Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/38523 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/variants/puff/overridetree.cb | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/mainboard/google/hatch') diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index 45d05d0928..d84b36986d 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -271,6 +271,10 @@ chip soc/intel/cannonlake chip drivers/net register "customized_leds" = "0x05af" register "wake" = "GPE0_DW1_07" # GPP_C7 + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)" + register "stop_delay_ms" = "12" # NIC needs time to quiesce + register "stop_off_delay_ms" = "1" + register "has_power_resource" = "1" device pci 00.0 on end end end # FSP requires func0 be enabled. -- cgit v1.2.3