From 3736127c979f52975bbad135548a36fd7585e7fd Mon Sep 17 00:00:00 2001 From: Rizwan Qureshi Date: Wed, 26 Dec 2018 19:02:09 +0530 Subject: mb/google/hatch: Enable SPI controller for Hatch Enable SPI controller(D31:F5). BUG=b:120914069 TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot Change-Id: I4d3acd3f31650d5b39927f8e3cfbb6187541653f Signed-off-by: Rizwan Qureshi Reviewed-on: https://review.coreboot.org/c/30438 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Patrick Rudolph --- src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/google/hatch') diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 0b3f469b77..a996a703b2 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -101,7 +101,7 @@ chip soc/intel/cannonlake device pci 1f.2 off end # Power Management Controller device pci 1f.3 off end # Intel HDA device pci 1f.4 off end # SMBus - device pci 1f.5 off end # PCH SPI + device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE end end -- cgit v1.2.3