From 299cb4bb8af9be08d1a5a39e23c6ff7cd96c1ad5 Mon Sep 17 00:00:00 2001 From: David Wu Date: Tue, 8 Sep 2020 15:30:29 +0800 Subject: mb/google/puff: Increase DPTF parameters for faffy Update critical and passive policy for TSR0. BUG=b:167477885 BRANCH=puff TEST=build and verify by thermal team Signed-off-by: David Wu Change-Id: I244e1b5cacabf5b73c47b4039ae150cd17fcd0fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/45169 Reviewed-by: Edward O'Callaghan Reviewed-by: Sam McNally Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/variants/faffy/overridetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mainboard/google/hatch') diff --git a/src/mainboard/google/hatch/variants/faffy/overridetree.cb b/src/mainboard/google/hatch/variants/faffy/overridetree.cb index c1bd1e4485..a05cb9d986 100644 --- a/src/mainboard/google/hatch/variants/faffy/overridetree.cb +++ b/src/mainboard/google/hatch/variants/faffy/overridetree.cb @@ -281,11 +281,11 @@ chip soc/intel/cannonlake chip drivers/intel/dptf ## Passive Policy register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 63, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000)" ## Critical Policy register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" - register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 78, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN)" ## Power Limits Control # 10-15W PL1 in 200mW increments, avg over 28-32s interval -- cgit v1.2.3