From b61f33cd484ece8c86acdce2740d0ab4018f3f30 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Wed, 18 Dec 2019 11:04:20 +1100 Subject: mainboard/google/puff: Enable pcie7 ep in dt Missing bus init for RTL8111H ethernet chip hanging on bus. V.2: Include admendments from Kangheui. BRANCH=none BUG=b:146437819 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I22aba312f183ea05eeb81d326ca0c05ce340a2e8 Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/37804 Tested-by: build bot (Jenkins) Reviewed-by: Kangheui Won Reviewed-by: Patrick Georgi --- src/mainboard/google/hatch/variants/puff/overridetree.cb | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/mainboard/google/hatch/variants/puff') diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index ca6c818128..d362b22770 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -103,6 +103,13 @@ chip soc/intel/cannonlake }, }" + # PCIe port 7 for LAN + register "PcieRpEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "1" + # Uses CLK SRC 0 + register "PcieClkSrcUsage[0]" = "6" + register "PcieClkSrcClkReq[0]" = "0" + # GPIO for SD card detect register "sdcard_cd_gpio" = "vSD3_CD_B" @@ -134,6 +141,7 @@ chip soc/intel/cannonlake end end #I2C #4 device pci 1a.0 on end # eMMC + device pci 1c.6 on end # PCI Express Port 7, RTL8111H Ethernet NIC. device pci 1e.3 off end # GSPI #1 end -- cgit v1.2.3