From 3de90d134494203556a81c47a6640ae101674114 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Tue, 4 Aug 2020 16:47:10 +0200 Subject: soc/intel/cnl: Set Heci1Disable depending on devicetree config MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently HECI1 gets enabled by the option HeciEnabled, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement/disablement of the HECI1 device. All corresponding mainboards were checked if the devicetree matches the HeciEnabled setting, and adjusted where necessary. Change-Id: I03dd3577fbe3f68b0abc2d196d016a4d26d88ce5 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/44177 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner --- src/mainboard/google/hatch/variants/noibat/overridetree.cb | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src/mainboard/google/hatch/variants/noibat') diff --git a/src/mainboard/google/hatch/variants/noibat/overridetree.cb b/src/mainboard/google/hatch/variants/noibat/overridetree.cb index cac7516000..2de90ec8e2 100644 --- a/src/mainboard/google/hatch/variants/noibat/overridetree.cb +++ b/src/mainboard/google/hatch/variants/noibat/overridetree.cb @@ -1,6 +1,4 @@ chip soc/intel/cannonlake - # Enable heci communication - register "HeciEnabled" = "1" # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1" @@ -284,6 +282,7 @@ chip soc/intel/cannonlake device i2c 4a on end end end # I2C #3, Realtek RTD2142. + device pci 16.0 on end # Management Engine Interface 1 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" -- cgit v1.2.3