From 309ccf74dd7c25874572c6a62ffc7042dcdadc66 Mon Sep 17 00:00:00 2001 From: Sumeet R Pawnikar Date: Sat, 9 May 2020 16:37:30 +0530 Subject: cannonlake: update processor power limits configuration Update processor power limit configuration parameters based on common code base support for Intel Cannonlake SoC based platforms. BRANCH=None BUG=None TEST=Built and tested on drallion system Change-Id: Iac6e6f81343fcd769619e9d7ac339430966834f6 Signed-off-by: Sumeet R Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/41235 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/hatch/variants/mushu/overridetree.cb | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'src/mainboard/google/hatch/variants/mushu') diff --git a/src/mainboard/google/hatch/variants/mushu/overridetree.cb b/src/mainboard/google/hatch/variants/mushu/overridetree.cb index 7bd1fac4e8..db86d68204 100644 --- a/src/mainboard/google/hatch/variants/mushu/overridetree.cb +++ b/src/mainboard/google/hatch/variants/mushu/overridetree.cb @@ -24,8 +24,10 @@ chip soc/intel/cannonlake register "FastPkgCRampDisableGt" = "1" register "FastPkgCRampDisableSa" = "1" - register "tdp_pl1_override" = "25" - register "tdp_pl2_override" = "44" + register "power_limits_config" = "{ + .tdp_pl1_override = 25, + .tdp_pl2_override = 44, + }" # Intel Common SoC Config #+-------------------+---------------------------+ -- cgit v1.2.3