From bb4b793f4a2a86cfbefbf9cd3b4f4b05b4183a0d Mon Sep 17 00:00:00 2001 From: Tarun Tuli Date: Tue, 25 Oct 2022 18:26:22 +0000 Subject: mb/google/hatch/var/kohaku: ensure FPMCU is power cycled on reset Leakage from the SPI CS line onto the FPMCU VDD rail was preventing the FPMCU from fully shutting down on AP reset. Instead of simply turning off the power rail, now ensure the CS line is not driven high until late in coreboot. This ensures it is completely off for the requisite minimum of 200ms (now measured at approx 1100ms). BUG=b:245953688 TEST=Confirmed FPMCU is still functional on Kohaku. Confirmed FpRebootPowerCycle unit test now passes BRANCH=Hatch Signed-off-by: Tarun Tuli Change-Id: I1e7e32f61c3ac1b3154d42821cc1dd4c5d3de303 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68819 Reviewed-by: Nick Vaccaro Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/variants/kohaku/gpio.c | 19 +++++++++++++++++-- src/mainboard/google/hatch/variants/kohaku/ramstage.c | 2 +- 2 files changed, 18 insertions(+), 3 deletions(-) (limited to 'src/mainboard/google/hatch/variants/kohaku') diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c index aa86932426..ef80800558 100644 --- a/src/mainboard/google/hatch/variants/kohaku/gpio.c +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -8,8 +8,6 @@ static const struct pad_config gpio_table[] = { /* A8 : PEN_GARAGE_DET_L (wake) */ PAD_CFG_GPI_SCI(GPP_A8, NONE, DEEP, EDGE_SINGLE, NONE), - /* A11 : PCH_SPI_FPMCU_CS_L */ - PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), /* A12 : FPMCU_RST_ODL */ PAD_CFG_GPO(GPP_A12, 0, DEEP), /* A16 : EMR_GARAGE_DET (notification) */ @@ -130,6 +128,23 @@ const struct pad_config *variant_early_gpio_table(size_t *num) return early_gpio_table; } +/* Set the FPMCU SPI CS line very late to workaround + * leakage of this line onto the VDD of the MCU. + */ +static const struct pad_config finalize_gpio_table[] = { + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), +}; + +/* + * GPIOs configured during the mainboard finalize + */ +const struct pad_config *variant_finalize_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(finalize_gpio_table); + return finalize_gpio_table; +} + /* * Default GPIO settings before entering non-S5 sleep states. * Configure A12: FPMCU_RST_ODL as GPO before entering sleep. diff --git a/src/mainboard/google/hatch/variants/kohaku/ramstage.c b/src/mainboard/google/hatch/variants/kohaku/ramstage.c index 176527b363..e861cfb34b 100644 --- a/src/mainboard/google/hatch/variants/kohaku/ramstage.c +++ b/src/mainboard/google/hatch/variants/kohaku/ramstage.c @@ -5,7 +5,7 @@ #include #include -void variant_ramstage_init(void) +void variant_final(void) { /* * Enable power to FPMCU, wait for power rail to stabilize, -- cgit v1.2.3