From 0d4200fef396fb0d1fbf28b4ced475fbf59b5b85 Mon Sep 17 00:00:00 2001 From: Philip Chen Date: Mon, 29 Apr 2019 10:18:24 -0700 Subject: soc/intel/cannonlake: Support different SPD read type for each slot Also clean up cannonlake_memcfg_init. The major changes include: (1) Add enum 'mem_info_read_type' to spd_info. (2) Add per-dimm-slot spd_info to cnl_mb_cfg. (3) Setup memory config for each slot independently. (4) Squash meminit_memcfg_spd(). BUG=chromium:960581, b:124990009 BRANCH=none TEST=boot hatch, hatch_whl, and kohaku Change-Id: I686a85996858204c20fd05ef24787a0487817c34 Signed-off-by: Philip Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/32513 Reviewed-by: Paul Fagerburg Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- .../google/hatch/variants/kohaku/memory.c | 29 +++++----------------- 1 file changed, 6 insertions(+), 23 deletions(-) (limited to 'src/mainboard/google/hatch/variants/kohaku') diff --git a/src/mainboard/google/hatch/variants/kohaku/memory.c b/src/mainboard/google/hatch/variants/kohaku/memory.c index 27ae3d8fb2..490124776e 100644 --- a/src/mainboard/google/hatch/variants/kohaku/memory.c +++ b/src/mainboard/google/hatch/variants/kohaku/memory.c @@ -15,7 +15,6 @@ #include #include -#include #include #include @@ -30,8 +29,8 @@ static const struct cnl_mb_cfg baseboard_memcfg = { * the index = pin number on SoC * the value = pin number on lpddr3 part */ - .dqs_map[DDR_CH0] = { 0, 1, 3, 2, 5, 7, 6, 4 }, - .dqs_map[DDR_CH1] = { 1, 3, 2, 0, 5, 7, 6, 4 }, + .dqs_map[DDR_CH0] = {0, 1, 3, 2, 5, 7, 6, 4}, + .dqs_map[DDR_CH1] = {1, 3, 2, 0, 5, 7, 6, 4}, .dq_map[DDR_CH0] = { {0xf, 0xf0}, @@ -40,7 +39,7 @@ static const struct cnl_mb_cfg baseboard_memcfg = { {0xf, 0x0}, {0xff, 0x0}, {0xff, 0x0} - }, + }, .dq_map[DDR_CH1] = { {0xf, 0xf0}, {0x0, 0xf0}, @@ -48,13 +47,13 @@ static const struct cnl_mb_cfg baseboard_memcfg = { {0xf, 0x0}, {0xff, 0x0}, {0xff, 0x0} - }, + }, /* Kohaku uses 200, 80.6 and 162 rcomp resistors */ - .rcomp_resistor = { 200, 81, 162 }, + .rcomp_resistor = {200, 81, 162}, /* Kohaku Rcomp target values */ - .rcomp_targets = { 100, 40, 40, 23, 40 }, + .rcomp_targets = {100, 40, 40, 23, 40}, /* Set CaVref config to 0 for LPDDR3 */ .vref_ca_config = 0, @@ -66,20 +65,4 @@ static const struct cnl_mb_cfg baseboard_memcfg = { void variant_memory_params(struct cnl_mb_cfg *bcfg) { memcpy(bcfg, &baseboard_memcfg, sizeof(baseboard_memcfg)); - /* - * GPP_F2 is the MEM_CH_SEL gpio, which is set to 1 for single - * channel skus and 0 for dual channel skus. - */ - if (gpio_get(GPP_F2) == 1) { - /* - * Single channel config: for kohaku, Channel 0 is - * always populated. - */ - bcfg->channel_empty[0] = 0; - bcfg->channel_empty[1] = 1; - } else { - /* Dual channel config: both channels populated. */ - bcfg->channel_empty[0] = 0; - bcfg->channel_empty[1] = 0; - } } -- cgit v1.2.3