From 119ace0908b66b718c4b581423309648b10e4bf7 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Wed, 2 Oct 2019 16:02:06 +0200 Subject: soc/intel/cnl: Configure FSP option PcieRpSlotImplemented Allow configuring FSP option PcieRpSlotImplemented. Also, update all related devicetrees and configure PcieRpSlotImplemented to keep the current behaviour. Change-Id: I6c57ab0ae50a37cd9a90786134e9056851a86a3c Signed-off-by: Nico Huber Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/39986 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/google/hatch/variants/kaisa/overridetree.cb | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src/mainboard/google/hatch/variants/kaisa/overridetree.cb') diff --git a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb index 67e62e7d08..dbf1851f32 100644 --- a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb @@ -394,8 +394,11 @@ chip soc/intel/cannonlake register "device_index" = "0" device pci 00.0 on end end + register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC - device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) + device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) + register "PcieRpSlotImplemented[10]" = "1" + end device pci 1e.3 off end # GSPI #1 end -- cgit v1.2.3