From a8a7374e843bae6c98ad242d2870bef6043d165d Mon Sep 17 00:00:00 2001 From: Wisley Chen Date: Thu, 19 Dec 2019 18:08:09 +0800 Subject: hatch: Fix FPMCU pwr/rst gpio handling for dratini/jinlon In https://review.coreboot.org/c/coreboot/+/37459 (commit fcd8c9e99e7f70e2b9494f2fa28a08ba13126daa) which moves power/reset pin control of FPMCU to var/board/ramstage, but does not implement it for dratini/jinlon. So, add it in dratini/jinlon. BUG=b:146366921 TEST=emerge-hatch coreboot Change-Id: I1b6dbe4ba0a1242aa64346410beed4152b4f457f Signed-off-by: Wisley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/37833 Reviewed-by: Tim Wawrzynczak Reviewed-by: Paul Fagerburg Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/variants/dratini/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard/google/hatch/variants/dratini/Makefile.inc') diff --git a/src/mainboard/google/hatch/variants/dratini/Makefile.inc b/src/mainboard/google/hatch/variants/dratini/Makefile.inc index 4ed09c9a76..0d577cde51 100644 --- a/src/mainboard/google/hatch/variants/dratini/Makefile.inc +++ b/src/mainboard/google/hatch/variants/dratini/Makefile.inc @@ -26,3 +26,4 @@ SPD_SOURCES += 16G_3200_4bg # 0b1001 bootblock-y += gpio.c ramstage-y += gpio.c ramstage-y += variant.c +ramstage-y += ramstage.c -- cgit v1.2.3