From 5e5167ed04082e0fe63db865382dc2021877ce3c Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 4 Jun 2019 14:43:58 +0530 Subject: mb/google/{hatch, sarien, arcada}: Make HECI1 chip config disable This patch is not actually disabling HECI1 as it requires a dedicated FSP UPD for WHL/CML SoC code to set this HECI1 chip config. Change-Id: Ia88f3315a9dc3365d0acc13ed887e7c596c97c91 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/33194 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/google/hatch/variants/baseboard') diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 61b712dbec..112c279fcb 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -28,7 +28,7 @@ chip soc/intel/cannonlake # Enable System Agent dynamic frequency register "SaGv" = "SaGv_Enabled" # Enable heci communication - register "HeciEnabled" = "1" + register "HeciEnabled" = "0" # Enable Speed Shift Technology support register "speed_shift_enable" = "1" # Enable S0ix -- cgit v1.2.3