From 1e3b2ce061626e6c5a7d7f89d40a854bac16f3d4 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Mon, 7 Dec 2020 01:28:59 +0100 Subject: soc/intel/cannonlake: Align SATA mode names with soc/skl MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Align the SATA mode names with soc/skl providing a consistent API. Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains identical. Change-Id: I54b48462852d7fe0230dde0c272da3d12365d987 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/48390 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier Reviewed-by: Michael Niewöhner --- src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/google/hatch/variants/baseboard') diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 31f6652401..5826f79ba9 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -20,7 +20,7 @@ chip soc/intel/cannonlake # FSP configuration register "SkipExtGfxScan" = "1" register "SataSalpSupport" = "1" - register "SataMode" = "Sata_AHCI" + register "SataMode" = "SATA_AHCI" register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[1]" = "1" # Configure devslp pad reset to PLT_RST -- cgit v1.2.3