From d49fafd531bb6ee3860da43ee0dc3bb81a135432 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Mon, 7 Dec 2020 01:33:42 +0100 Subject: mb/*: Remove SATA mode config for CNL based mainboards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SATA_AHCI is already the default mode for CNL based mainboards. Therefore, remove its configuration from all related devicetrees. Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains identical. Change-Id: I814e191243224a4b021cd7d4c1b611316f1fd1a4 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/48391 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner --- src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 1 - 1 file changed, 1 deletion(-) (limited to 'src/mainboard/google/hatch/variants/baseboard/devicetree.cb') diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 5826f79ba9..7d9d1e64ca 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -20,7 +20,6 @@ chip soc/intel/cannonlake # FSP configuration register "SkipExtGfxScan" = "1" register "SataSalpSupport" = "1" - register "SataMode" = "SATA_AHCI" register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[1]" = "1" # Configure devslp pad reset to PLT_RST -- cgit v1.2.3